Phd in Physics

Introduction to FPGA Programming Using Xilinx Vivado and VHDL

Introduction to FPGA Programming Using Xilinx Vivado and VHDL

Academic year 2024/2025

Sommario del corso

• Course objectives
• Results of learning outcomes
• Program
• Course delivery
• Learning assessment methods
• Support activities
• Class schedule
• Teaching tools
• Course card

Course objectives

The course aims to provide to PhD students specializing in experimental Physics an exhaustive introduction to the usage of Field Programmable Gate Array (FPGA) devices to implement control systems and data acquisition (DAQ) systems for sensors and actuators. The Hardware Description Language (HDL) used in the course will be VHDL.

Results of learning outcomes

Knowledge and understanding

Understanding of fundamental aspects related to the design, simulation and implementation of digital circuits targeting Xilinx FPGA devices using the VHDL hardware description language and the professional CAD environment Xilinx Vivado.

Applying knowledge and understanding

Design, simulation and implementation of digital circuits targeting Xilinx FPGA devices using the Verilog HDL and the professional CAD environment Xilinx Vivado.

Program

The course provides an in-depth introduction to digital design and FPGA programming using Xilinx Vivado and the VHDL Hardware Description Language (HDL). The main topics covered in the course are:

• VHDL syntax fundamentals, HDL design flow
• logic values, resolved vs. unresolved logic values, 3-state logic, buses and endianess
• review of boolean algebra
• introduction to Xilinx Vivado simulation and implementation flows
• design and simulation of combinational circuits with VHDL examples (multiplexers, decoders, encoders etc.)
• FPGA architectures overview and basic building blocks (fabric, BEL, LUT, CLB, CLA, slices, IOBs, hard-macros)
• introduction to Xilinx Design Constraints (XDCs)
• sequential circuits, latches and FlipFlops
• counters, registers, Pulse-Width Modulation (PWM), shift-registers, FSM, FIFOs, RAM/ROM
• advanced Xilinx Design Constraints (XDCs) and timing fundamentals
• synchronous design good and bad practices, example Vivado IP flows (clock wizard, FIFO compiler)
• gate-level simulations with back-annotated delays (SDF)
• practical implementation and test of small digital systems targeting a Xilinx Artix-7 FPGA device

Course delivery

The course is organized in form of hands-on "virtual laboratories" to introduce fundamental concepts in FPGA design and simulation using VHDL and Xilinx Vivado. Each "lab" consists of step-by-step instructions to guide the student in running the simulation and implementation flows using Xilinx tools from the command-line. The only requirement for these labs is to have a personal computer with all necessary development tools properly installed and configured.

In order to maximize the participation to the course all introductory theoretical/hands-on lectures will be held remotely using the Webex platform. All lectures will be also video-recorded.

The virtual room to attend the lectures is accessible at the following link:

https://unito.webex.com/meet/luca.pacheropen_in_new

All HDL sources and scripts required to run the FPGA programming flows (HDL simulations, synthesis/place-and-route and firmware download) are tracked on GitHub and are available at the following address:

https://github.com/lpacher/fphdopen_in_new

Before attending the introductory lectures all students are requested to install all necessary software components as extensively described in this pageopen_in_new.

For interested students, virtual laboratories will be then completed by practical examples in the electronics lab in order to let students to physically experiment with a real FPGA development board and digital circuits using real hardware and instrumentation.

Learning assessment methods

No exam foreseen for this course. However attending ≥ 70% of lecturing hours is mandatory in order to get course credits validation.

Support activities

On the GitHub repository of the course students can freely access all  Webex links to past video-recorded lecturesopen_in_new.

Class schedule

• Teaching material
• Exams and finals
• Class schedule
• Go to Moodle
• Register for the course
• Enrolled students
• Invia email agli studenti registrati
• Export table