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Introduction to FPGA Programming Using Xilinx Vivado and VHDL

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Introduction to FPGA Programming Using Xilinx Vivado and VHDL

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Academic year 2022/2023

Teacher
Luca Pacher (Lecturer)
Degree course
PhD in Physics
Year
1st year 2nd year 3rd year
Teaching period
Second semester
Type
Elective
Credits/Recognition
4 CFU
Course disciplinary sector (SSD)
FIS/01 - experimental physics
Delivery
Traditional
Language
English
Attendance
Obligatory
Prerequisites

Familiarity with Linux basic shell commands to work with files and directories (pwd, cd, ls, cp, mv, mkdir, rm etc.), with the GNU Makefile (make) and with a text editor for source coding is assumed.

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Sommario del corso

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Course objectives

The course aims to provide to PhD students specializing in experimental Physics an exhaustive introduction to the usage of Field Programmable Gate Array (FPGA) devices to implement control systems and data acquisition (DAQ) systems for sensors and actuators. The Hardware Description Language (HDL) used in the course will be VHDL.

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Results of learning outcomes



Knowledge and understanding

Understanding of fundamental aspects related to the design, simulation and implementation of digital circuits targeting Xilinx FPGA devices using the VHDL hardware description language and the professional CAD environment Xilinx Vivado.



Applying knowledge and understanding

Design, simulation and implementation of digital circuits targeting Xilinx FPGA devices using the Verilog HDL and the professional CAD environment Xilinx Vivado.

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Course delivery

 

The course is organized in form of hands-on "virtual laboratories" to introduce fundamental concepts in FPGA design and simulation using VHDL and Xilinx Vivado. Each "lab" consists of step-by-step instructions to guide the student in running the simulation and implementation flows using Xilinx tools from the command-line. The only requirement for these labs is to have a personal computer with all necessary development tools properly installed and configured.

In order to maximize the participation to the course all introductory theoretical/hands-on lectures will be held remotely using the Webex platform. All lectures will be also video-recorded.

The virtual room to attend the lectures is accessible at the following link:

https://unito.webex.com/meet/luca.pacher

All HDL sources and scripts required to run the FPGA programming flows (HDL simulations, synthesis/place-and-route and firmware download) are tracked on GitHub and are available at the following address:

https://github.com/lpacher/fphd

Before attending the introductory lectures all students are requested to install all necessary software components as extensively described in this page.

For interested students, virtual laboratories will be then completed by practical examples in the electronics lab in order to let students to physically experiment with a real FPGA development board and digital circuits using real hardware and instrumentation.

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Learning assessment methods

No exam foreseen for this course. However attending ≥ 70% of lecturing hours is mandatory in order to get course credits validation.

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Support activities

On the GitHub repository of the course students can freely access all  Webex links to past video-recorded lectures.

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Program

The course provides an in-depth introduction to digital design and FPGA programming using Xilinx Vivado and the VHDL Hardware Description Language (HDL). The main topics covered in the course are:

  • VHDL syntax fundamentals, HDL design flow
  • logic values, resolved vs. unresolved logic values, 3-state logic, buses and endianess
  • review of boolean algebra
  • introduction to Xilinx Vivado simulation and implementation flows
  • design and simulation of combinational circuits with VHDL examples (multiplexers, decoders, encoders etc.)
  • FPGA architectures overview and basic building blocks (fabric, BEL, LUT, CLB, CLA, slices, IOBs, hard-macros)
  • introduction to Xilinx Design Constraints (XDCs)
  • sequential circuits, latches and FlipFlops
  • counters, registers, Pulse-Width Modulation (PWM), shift-registers, FSM, FIFOs, RAM/ROM
  • advanced Xilinx Design Constraints (XDCs) and timing fundamentals
  • synchronous design good and bad practices, example Vivado IP flows (clock wizard, FIFO compiler)
  • gate-level simulations with back-annotated delays (SDF)
  • practical implementation and test of small digital systems targeting a Xilinx Artix-7 FPGA device

Suggested readings and bibliography

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Slides and additional course material provided by the teacher. It is not required to buy a specific book for this course. Some useful references are:

  • B. Mealy and F. Tappero, Free Range VHDL (open source)
  • M. Field, Introducing the Spartan 3E FPGA and VHDL (open source)
  • C.H. Roth Jr, Digital Systems Design Using VHDL - Bostom PWS
  • P.P. Chu, FPGA Prototyping By VHDL Examples - Wiley
  • R.E. Haskell, D.M. Hanna, Introduction to Digital Design Using Digilent FPGA Boards - LBE Books
  • S. Churiwala (Editor), Designing with Xilinx FPGAs Using Vivado - Springer
  • S. Gangadaran and S. Churiwala, Constraining Designs for Synthesis and Timing
    Analysis: A Practical Guide to Synopsys Design Constraints (SDC)
    - Springer

 

It might be of interest to mention that the book Introduction to Digital Design Using Digilent FPGA Boards is  accompanied by a collection of 112 video-lectures given by one author and freely available on the YouTube channel.

All code sources introduced and discussed during hands-on lectures are available on the GitHub repository of the course.



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Class schedule

Lessons: from 26/06/2023 to 07/07/2023

Notes:

In order to maximize the participation to the course all introductory theoretical/hands-on lectures will be held remotely using the Webex platform. All lectures will be also video-recorded.

The virtual room to attend the lectures is accessible at the following link:

https://unito.webex.com/meet/luca.pacher



Day Time Class Notes
26/06/2023 14-15 Webex Course schedule definition
28/06/2023 11-13 Webex Lecture record 1 
29/06/2023 11-13 Webex Lecture record 2 
30/06/2023 11-13 Webex Lecture record 3 
03/07/2023 11-13 Webex Lecture record 4 
04/07/2023 11-13 Webex Lecture record 5 
05/07/2023 11-13 Webex Lecture record 6 
06/07/2023 11-13 Webex CANCELED (overlap with exams)
07/07/2023 11-13 Webex Lecture record 7 
10/07/2023 11-13 Webex Lecture record 8 




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